Hello everyone. I am Yoshimura (@alterakey). ATL has been conducting an inquiry into FPGAs.

High-level synthesis and OpenCL

As was explained in the preceding document, low-layer design goes hand-in-hand with FPGA development. Consequently, FPGA development is a substantially more involved process than when processors are used.

However, a method known as “high-level synthesis” has recently become usable. High-little development is a method that automatically produces low-layer designs from the implementation of algorithms. This automatic production of low-layer designs makes the implementation of algorithms in FPGAs easier for developers.

High-level synthesis can be performed by means of OpenCL. OpenCL is a parallel computing library that is being standardized by Khronos Group. By using OpenCL, computing (kernels) can be executed in parallel independently of the environment. The independence of kernels from their environment means that anything can take part in the joint execution of the kernels no matter what it is. The kernels are written in the OpenCL C programming language. OpenCL C is a language that is an extension of simple OpenCL.

Note
See our official website for details on OpenCL.

In high-level synthesis that uses OpenCL, FPGA chips are configured as computing devices that can use OpenCL. During computing, OpenCL is used from the system (host) to run devices.

Development Environment

Use of high-level synthesis requires a dedicated development environment (a high-level synthesis environment). High-level synthesis environments differ depending on the FPGAs and boards used. A “board” is a substrate with chips and peripheral devices installed. The FPGA used in this document is Altera’s Cyclone V SoC. DE1-SoC (made by Terasic) is used in the board.

Altera’s two high-level synthesis environments consist of high-level synthesis SDK and BSP. High-level synthesis SDK is a package that combines together all the development tools necessary for a high-level synthesis environment. BSP is a file group that differs from board to board, and is installed and used in high-level SDK. This can be explained as follows.

Additionally, in order to use Altera’s high-level synthesis environment in a Windows environment, two more procedures (UNIX-like environment setup and cross-compilation environment setup) are necessary in addition to the two aforementioned installations. A UNIX-like environment is the environment that allows for the use of UNIX-type tools with Windows. MSYS2 is the environment used in this document. A cross-compilation environment is an environment that builds post-side programs. This can be explained as follows.

Note
This document does not touch upon development environment license settings. For details, see the installation and license manual.

Installing High-level synthesis SDK

High-level synthesis SDK can be obtained from Altera. It requires a licensing fee.

Note

I have not looked into whether free trial use of high-level SDK is possible.

You must register with Altera to obtain high-level SDK. For details on registration, referred to the previous document.

You can access the “My Altera” support portal once registration is completed.

Login to My Altera, and select “Download Quartus II” from the lower menu. Once selected, you will transition to a download center.

Note
The name of Quartus II has been changed to Quartus Prime.

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Once you have transitions, scroll down and click the “Altera SDK for OpenCL” button.

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You can choose a downloading method once you click the “Download” button. You can choose from two types of downloading methods: direct download and download manager. We recommend that you choose download manager. Download manager requires more effort to perform installation in comparison with direct download, but there will be fewer problems with downloading.

Next, select the image to download. The downloadable images include Windows SDK and Linux SDK. Windows is used in this document. Click the “Download” located in the bottom to start downloading.

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Install the program once you have downloaded it. The installation procedure has been omitted from this document. For the procedure, refer to the Altera SDK for OpenCL Start Guide.

BSP Installation

BSP can be obtained from evaluation board manufacturers. The DE1-SoC used in this document can be downloaded from Terasic.

Terasic’s website pertaining to DE1-SoC can be viewed at the following link.

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Select [Resources] from the menu in the upper right of the displayed website to display the downloadable materials. BSP consists of three files under “BSP(Board Support Package) for Altera SDK OpenCL 14.0.” The user manual zip archive is the file you should download.

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Install the program once you have downloaded it. The installation procedure has been omitted from this document. For this procedure, see DE1-SoC OpenCL User Manual.

UNIX-like Environment Settings

A UNIX-like environment is the environment that allows for the use of UNIX-type tools with Windows. In a href=”http://atl.recruit-tech.co.jp/blog/3997/”>the preceding document, Altera’s FPGA development environment was described as an integrated development environment. However, when using high-level synthesis, an integrated development environment cannot be used. This is because high-level synthesis systems are not yet compatible with integrated development environments. Also, high-level synthesis systems are derived from UNIX. Therefore, in order to perform high-level synthesis in a Windows environment, it is necessary to prepare a UNIX-like environment.

MSYS2 is the UNIX-like environment used in this document. MSYS2 is a relatively lightweight UNIX -like environment that has been also adopted as a Git for Windows operating base.

You can download MSYS2 from our official website. Install the program once you have downloaded it. The installation procedure has been omitted from this document. See the MSYS2 official website for details on the installation procedure.

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Next, create a path to the development environment in the MSYS2 shell. To create a path to the development environment, start up MSYS2, and execute the following command. After executing the command, it will be applied when the shell is restarted.


$ echo 'export PATH=/c/altera/15.0/hld/bin:$PATH' >> ~/.profile

Cross-compilation Environment Setup

A cross-compilation environment is an environment that builds host-side programs. Gcc-linaro-arm-linux-gnueabihf-4.8-2014.04 is the cross-compilation environment used in this document. Gcc-linaro-arm-linux-gnueabihf-4.8-2014.04 is recorded to Linaro 14.04 as part of linaro-toolchain-binaries 4.8.

Download cc-linaro-arm-linux-gnueabihf-4.8-2014.04 (hereinafter referred to as “the cross compilation environment” from the llinaro-toolchain-binaries 4.8 release page. This document uses a Windows environment, so the file you should download is gcc-linaro-arm-linux-gnueabihf-4.8-2014.04_win32.zip.

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Install the program once you have downloaded it. To install the file, extract the file to the appropriate directory.

Next, create a path to the cross-compilation environment in the MSYS2 shell. To create a path to the cross-compilation environment, start up MSYS2, and execute the following command. The following is an example of a command to create a path. This example presumes that the cross compilation environment has been extracted to C:\Users\taky\bin\gcc-linaro-arm-linux-gnueabihf-4.8-2014.04_win32. After executing the command, it will be applied when the shell is restarted.


$ echo 'export PATH=/c/Users/taky/bin/gcc-linaro-arm-linux-gnueabihf-4.8-2014.04_win32/bin:$PATH' >> ~/.profile

Board Initial Setup

For the DE1-SoC used in this document, a different initial setup is required from when high-level synthesis is used. There are two settings in initial setup when high-level synthesis is used: DIP switch setup and creation of an SD card (boot card) for host startup.

DIP switch setup is a step to set up a board for high-level synthesis evaluation. For DE1-SoC, the MSEL must be set. The MSEL is a small DIP switch located on the underside of the substrate. Set the MSEL4~0 to ON-OFF-ON-OFF-ON (01010).

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Boot card creation requires an SD card with a capacity of 4 GB or greater. Use Win32 Disk Imager to write a host startup image file to the prepared SD card. The host startup image file will be created when the BSP is installed. In this document, the file is located in C:\altera\15.0\hld\board\de1soc\linux_sd_card_image.img.

Try to launch the board by inserting the boot card into it. The startup image file enables the serial console. The serial console is a host function that can perform control via serial ports. There are two procedures for connecting to the serial console. First, connect to the USB serial port on the DE1-SoC to the development machine with a USB cable. Then, use TeraTerm or other such terminal software to connect to the USB serial port. The serial port settings necessary for connection are as follows:

Baud rate

115200

Data bit

8 bit

Parity

None

Stop bit

1 bit

Note
You can also download the USB serial port driver from http://www.ftdichip.com/Drivers/VCP.htm.

Once you have connected successfully, the system log will flow concomitantly with the host startup. Finally, a login prompt will appear. The following is an example of a login prompt.

Confirm that the username “root” has been entered.

This concludes the initial.

Sample

Let’s try performing some FPGA development using high-level synthesis. The sample project (“sample”) used in this document is located at https://bitbucket.org/taky/fpga-hld-sample. To execute this sample, write the text string “hello world” to the console.

Sample OpenCL Kernel (device/hello_world.cl).

There are three operations involving the sample: Building, relaying, and execution.

Building

First, perform building. There are two things to be built: the host side program and the device side flow. To perform building, input commands for both into the MSYS2.

First, build the host side program. The following command is necessary to perform building.

Next, build the device-side flow. The following command is necessary to perform building.

Note

Building the device-site flow is a time-consuming process. For the sample in this document, the benchmark time requirement for building the device-site flow is about 15 minutes using a Core i7 4790.

Configuration File Setup in the Boot Card

Actually running the sample requires another setting. That would be configuration file set up in the boot card. Configuration file set up is only performed once.

The configuration file that should be set up is /opencl.rbf in the boot card. To set up the configuration file, right the configuration file using the top.rbf file located in the directory that was created when you built the device-side flow. Once you build the device-side flow, a directory with the same name (“aocx”) as the flow file will be created in the same location as the flow file.

The following is an example of the command used for overwriting. This example presumes two conditions. The first is that the sample is located in C:\Users\taky\works\fpga\hello_world. The second is that the boot card is located in the G driveG drive drive

This concludes configuration file setup in the blue card.

Relaying

Relaying is performed with the scp command. The scp command is a command for safely relaying files and directories.

You must know the IP address of the host when relaying to the host using the scp command. Start the host to determine the IP address of the board. To start the host, insert the boot card into the board, connect the USB serial port and ethernet, and turn on the power supply. Once the host has started, login to the serial console as “root.” Once you have logged in, look for the IP address. Use the ifconfig commands to determine the IP address. The following is an example of command execution. “Eth0” in the example is an ethernet interface name.

The address (for example, 192.168.100.16) written after inet addr: is the IP address.

Once you have determined the IP address, perform relaying with the scp command. There are two files that you should relay: the host-side execution file and the device-side flow file. The following is an example of a command used for relaying.. In the example, it is presumed that the IP address of the host is 192.168.100.16.

Startup

Two procedures are required to start the relayed sample: OpenCL environment initialization and execution.

To initialize the OpenCL environment, first login as “root”. After login, input the following command.

Note

Initialization must be performed whenever you log in.

To execute initialization, run the host-side execution file. In the sample in this document, the start command is “./hello”. The following is an example of the results of its execution.

Synopsis

This document explained high-level synthesis using FPGAs. High-level synthesis is a recently-devised FPGA development method. Because low layer design is automatically performed in high-level synthesis, it is characterized by the ease with which it can implement algorithms themselves in comparison with earlier FPGA development methods. Next, we touched upon the environment for performing high-level synthesis. To perform high-level synthesis in a Windows environment, it is necessary to add a UNIX -like environment or a cross compilation environment in addition to installing Altera’s development environment. The sample was created with high-level synthesis in the finally prepared development environment and made to operate.

For brevity’s sake, this document did not touch upon the details of the sample’s source code. If you took a look at the sample’s source code, I think you would see that it has a structure that resembles that of an ordinary OpenCL program. In particular, if you were to look at the source code of the OpenCL kernel, I think you would see that it using a very familiar type of algorithm.

Next time, we will deal with high-level applications. That is all for now.

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