Hello everyone. I am Yoshimura (@alterakey). ATL has been conducting an inquiry into FPGAs.

What is an FPGA?

An FPGA (Field Programmable Gate Array) is a rewritable custom chip. A custom chip is a calculation circuit that has been specialized for a certain application. It sacrifices the versatility of a calculation circuit in order to achieve high processing speeds and electrical efficiency. A familiar example of its use would be the control section of a high-end layer 2 switch.

Algorithm Implementation

Processors (CPUs and GPUs) and FPGAs implement algorithms to perform processing. Algorithms are implemented through the use of programs. However, processors and FPGAs differ in the programs they require. This can be explained as follows.

Processors regard programs as series of instructions. When a processor is given a series of instructions, it reads them sequentially to perform an operation. Thus the implementation of algorithms in development that uses processes involved correctly listing instructions so that the desired process will be performed.

However, for FPGAs, programs are configuration information. Configuration information consists of information such as the settings, hard wiring, and signal line configurations of internal units. This information is referred to as “flow.” When flow is provided to an FPGA, internal units undergo configuration changes, and the flow of signals (“the pipeline”) is organized. Thus the implementation of algorithms in FPGA development amounts to the organization of pipelines to perform the desired processes.

Flow is like an electronic circuit diagram. The implementation of a given algorithm as a flow requires design that incorporates careful consideration of hardware. Design that incorporates careful consideration of hardware is low-layer design that encompasses everything from what pin performs signal inputs and outputs to the ways signals are processed. Signal timing is a problem that cannot be ignored in low-layer design, so design that focuses on minute details is desirable. Consequently, algorithm implementation in FPGA development is a substantially more involved process than when processors are used.

Development Environment

Let’s take a look at some actual FPGA development. FPGA development requires a development environment. Altera and Xilinx are the two companies at the vanguard of FPGA -related technology. This document explains Altera’s FPGA development environment.

Altera’s development environment is an integrated development environment. Different boards can be used in the same development environment provided they have Altera FPGA’s. A “board” is a substrate with chips and peripheral devices installed.

The FPGA used in this document is Altera’s Cyclone V SoC. DE1-SoC (made by Terasic) is used in the board.

Installation of the Development Environment

The development environment is Quartus II. It is obtained from Altera. Both free versions and paid versions of development tools can be obtained. This document describes free versions that can be easily obtained for testing purposes.

The name of Quartus II has been changed to Quartus Prime.

You must register with Altera to obtain the free version of Quartus II. Registration requires an email address.


You can fill out the registration form once your email address is confirmed. In the registration form, you must enter your address, name, telephone number, affiliation, occupation, scale of business, evaluation goals, evaluation period, desired username, and desired password, and agree to the terms of service. The evaluation period you enter into the form is only a declaration of how long you intend to evaluate Quartus Prime. You can continue to use Quartus Prime even after the evaluation period you declare on the form has expired.


You can access the “My Altera” support portal once registration is completed.

Login to My Altera, and select “Download Quartus II” from the menu on the right. Once selected, you will transition to a download center.


After you transition to the download center, click the “Download” button beside “Quartus II Web Edition.”


You can choose an OS downloading method once you click the “Download” button. There are two operating systems to choose from: Windows and Linux. Windows is used in this document. You can choose from two types of downloading methods: direct download and download manager. We recommend that you choose download manager. Download manager requires more effort to perform installation in comparison with direct download, but there will be fewer problems with downloading.


Install the program once you have downloaded it. The installation procedure has been omitted from this document. For the procedure, refer to the Quick Start Guide.

Board Initial Setup

The board requires an initial set up to use. Initial setup is a step to set up a board for evaluation.

For the DE1-SoC used in this document, the required initial setup is the DIP switch (MSEL) setup. MSEL is located on the underside of the substrate. Set MSEL4~0 to OFFONONOFFON(10010).

Start the board to confirm whether the board has been set up properly for evaluation. If the board is started successfully, ascending numeric values will appear on it.


Board Connection

To perform development, the board must be connected to a development machine. Use a USB A-B cable to connect the board to a development machine. Once the board starts up after being correctly connected to the development machine, the necessary drivers will be installed in the development machine.

Sample Project

Let’s try performing some actual FPGA development. This document explains development by means of a sample project (hereinafter referred to as the “sample”). The sample described in this document is recorded on the system CD that comes with the board. The directory location in which the sample is recorded is /Demonstrations/FPGA/my_first_fpga.

If you have no system CD, you can download an image of it from http://www.terasic.com/downloads/cd-rom/de1-soc/[DE1-SoC CD-ROMs].

Button input becomes possible once the sample is started. There are two buttons that can be used for input: KEY0 and KEY1. When you press KEY1, the LED will flicker only while the button remains pressed. When you press KEY1 and KEY0 simultaneously, the speed of the flickering of the LED will slow down only while the buttons remained pressed.


To perform building, open the sample in an integrated development environment, and press the playback button in the upper part of the screen.


It will take some time for the procedure to be completed. The sof file is created when the procedure is completed.



To perform programming, start the program are located in the upper part of the screen of the integrated development environment.

There are two programming methods: JTAG and AS. The difference between the two is and whether flow continues after the power supply has been cut off (nonvolatility). For the sake of simplicity, this document describes a procedure that uses JTAG with no flow remaining after the power supplies been cut off.



Using the program requires certain settings. These two required settings are board selection and board configuration detection.

To select a board, click the “Hardware Setup…” button. When the button is clicked, a dialog will appear. Allocate [DE-SoC[USB-1]] as the [Currently selected hardware].


Next, detect the board configuration. To detect the board configuration, click the “Auto Detect” button, and select the chip model. For the DE1-SoC used in this document, you should select the [5CSEMA5] chip model.


When a dialogue appears in the detection results asking whether to replace the configuration, select “Yes.” When detection is completed, two entries will appear as a list.


Next, perform programming. Programming requires three procedures: reading the sof file, specifying what is to be programmed, and starting the programming.

To read the sof file, select the entry that indicates the FPGA chip from among the entries that appear after detection is completed. The entry that indicates the FPGA chip starts with [5CSEMA5]. After you select the entry, you can click the [Change File] button on the left side menu. When you click the [Change File] button, the sof selection dialog will open. When you select the sof file, the file name is entered in the [File] column.

Next, specify what is to be programmed. To specify what is to be programmed, check the [Program/Configure] checkbox located to the right of the entry that read the sof file. Once that which is to be programmed is specified, the [Start] button on the right side menu will be enabled.


Finally, start programming. Click the [Start] button in the right side menu to start the programming operation. You can see how the operation is progressing in the data located in the upper right of the screen. Flow will start automatically when the operation is completed.


In this document we have examined the characteristics of FPGAs. An FPGA is a calculation circuit specialized for a specific domain. An FPGA differs from processor in that it does not use commands. To implement an algorithm with an FPGA, assemble a pipeline to perform the desired signal processing. Low-layer design is indispensable to pipeline assembly. Next, to view the actual FPGA development, an FPGA development environment from Altera has been installed. The sample was built in the installed development environment, and the FPGA was programmed and made to operate.

For brevity’s sake, this document did not touch upon the details of the sample’s source code. I think that if one were to view the source code of the sample, it would overemphasize the differences with development that uses a processor.

Next time, we will deal with high-level synthesis. High-level synthesis is a recently-devised FPGA development method. That is all for now.